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USING THE DIL/NetPC DNP/1486-3V I/O EXPANSION BUS

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For the interface to external I/O devices, the DIL/NetPC DNP/1486-3V offers the I/O Expansion Bus signals. This bus consist of 8 data bits, 4 address bits and 12 control signals. The control signals are 4 programmable chip select outputs, 5 programmable interrupt inputs, I/O Read, I/O Write and a I/O Channel Ready signal.

The individual signals at this bus allow a very simple interface to external components. It is to be considered, however, that the DIL/NetPC DNP/1486-3V is a 3.3 volt-based system. The output levels are derived from the 3.3 volt supply voltage.

All inputs of the DIL/NetPC DNP/1486-3V I/O Expansion Bus can be driven by external 5 volt components. With other words: The inputs of the I/O Expansion Bus are 5 volt tolerant. Please absolutely note that this does not apply to all input pins of the DIL/NetPC DNP/1486-3V.

The 8-bit data SD7...SD0 is available at the I/O Expansion Bus with the Pins 56 - 63. The Pins 52 - 55 are four address bits SA3 ... SA0. Please consider, that a DIL/NetPC DNP/1486-3V-based system donīt need external address decoders for chip select generation to external components. With the pins 45 - 48 the DIL/NetPC DNP/1486-3V offers four programmable chip select signals CS4 ... CS1. The four address lines are used therefore only for the internal register selection in external devices.

For the activation of I/O Expansion Bus Read/Write cycles the DIL/NetPC DNP/1486-3V has the signals IOR (I/O Read, pin 50, low activ) and IOW (I/O Write, pin 51, low activ). The timing of one Read/Write bus cycle can be influenced about IOCHRDY at the pin 49.

Figure 1: Read Timing of the I/O Expansion Bus

For external interrupts to the DIL/NetPC DNP/1486-3V, stand at the pins 40 ... 44 the programmable interrupt inputs INT5 to INT1 for the disposal. The figure 1 shows clearly the timing with the read access (I/O Expansion Bus Read Cycle) on external I/O devices. Figure 2 includes the same information for the write access (I/O Expansion Bus Write Cycle).

Figure 2: Write Timing of the I/O Expansion Bus

The following table includes the timing values for the individual times of the figure 1 (I/O Expansion Bus Read Cycle) and figure 2 (I/O Expansion Bus Write Cycle). All values are to be considered as "typical". The entire timing for write and read accesses at the I/O Expansion Bus of a DIL/NetPC DNP/1486-3V is in approximately compatible to the ISA bus (see also Dual UART Expansion, PDF document - size 114.120 bytes).